1. Field of the Invention
The present invention relates to static random access memory devices. More particularly, the present invention relates to a static random access memory cell which may be reliable read and written.
2. The Prior Art
The implementation of Static Random Access Memory (SRAM) cells from cross-coupled inverters using CMOS logic is well known in the prior art. Cell reliability is an important design consideration for SRAM cells. One way of evaluating the reliability of an SRAM memory cell is to observe the content of the cell as it is accessed. During a read operation, it is desired that the data contained in the memory cell remains unchanged. In addition, during a write operation it is important that the intended data is actually written into the memory cell.
A typical SRAM cell is configured from cross-coupled inverters coupled to a bitline through a pass transistor connected to an output node of the cell comprising the common drain connection of the complementary MOS transistors of one of the inverter pairs. The SRAM cell is accessed for a read or write operation by applying a voltage potential to the gate of the pass transistor so that the content of the cell may be read or altered. Ensuring that writes occur as intended and that reads do not change the content of the SRAM cell depends upon the sizing of the inverter transistors and the pass transistor. The appropriate sizing of these transistors, however, presents a significant design problem in that the ideal sizing of these transistors for a read operation is in conflict with the ideal sizing for a write operation.
The prior art has provided numerous compromises to attempt to deal with this design problem. An illustrative prior art approach is set forth in U.S. Pat. No. 4,750,155, which provides three suggested solutions to this problem. According to a first approach, the rise time of the voltage to the gate of the pass transistor is greatly increased. To increase the rise time of the pass transistor, a weak address driver pull-up transistor is used. This reduces the coupling of the bitline to the output node of the inverter, however, it also severely limits performance of the memory cell.
According to a second approach, the bitline is precharged during a read operation to a trigger voltage for the inverter coupled to the output node of the cell. In doing so, the voltage at the output node of this inverter, which for a logic low is set by the division of the voltage between the voltage on the bitline and ground by a resistive divider comprising the channel on resistances of the pass transistor and the N-Channel MOS transistor in the inverter, is kept lower than the trigger voltage, thus ensuring that the voltage at the output node of the inverter remains low. Conversely, for a logic high at the output node of the inverter, which is set by the division of the voltage between the voltage on the bitline and Vcc by the resistive divider comprising the equivalent channel on resistances of the pass transistor and the P-Channel MOS transistor in the inverter, the voltage at the output node of the cell is kept higher than the trigger voltage, thus ensuring that the cell output voltage remains high.
This approach has several severe limitations. The first limitation is that it is critical that the trigger voltage be accurately maintained at the inverter trigger point for all memory cells, across all process variations. Since this scheme uses a reference inverter to set the trigger voltage for each bitline, the same trigger voltage is applied to each memory cell along the bitline. Due to the normally-encountered process variations among inverters along the bitline, the trigger point of each of the memory cells will be slightly different, and as such will not match the trigger voltage on the bitline. A greater limitation is that the noise margin on the bitline is approximately zero. Hence, any bitline noise or coupling may disturb the cell content during a read operation, and will make sensing the bitline level difficult.
According to a third approach disclosed in this patent, the channel resistance of the pass transistor is varied depending upon whether a read or write operation occurs. The channel resistance of the pass transistor is varied by changing the voltage level supplied to its gate. During a read operation the gate voltage of the pass transistor is dropped to a trigger voltage level corresponding to the trigger point of a reference inverter. This scheme addresses some of the problems present in the above described approaches, however, it has drawbacks of its own. One limitation is that the size of the inverters in the memory cell and the corresponding reference inverter are critical, and these sizes are affected by process variations. A second limitation is that this approach significantly increases the layout area due to the fact that each bitline needs a trigger voltage level supply generator and a modified driver.
There remains a need for an SRAM memory cell which overcomes these drawbacks of prior art SRAM memory cells. It is an object of the present invention to provide such a memory cell.